Overview of ESTC 2024 Professional Development Courses on September 11, 2024

Short Courses can be booked together with the conference ticket through our online registration at www.conftool.net/estc2024

8:30 am – 10:30 am: “Multiphysics and Multiscale Modeling and Analysis of Advanced IC Packaging and Systems”

Course instructor: Rajen Murugan

Dr. Rajen Murugan specializes in developing multiphysics system co-design modeling and simulation methodologies for advanced IC packaging and systems. He is currently a Distinguished Member of the Technical Staff (DMTS) with Texas Instruments, Inc. He has 31 granted (US and Canada) patents and 72 under review at the USPTO. He has published over 50 papers in peer-reviewed IEEE journals and conferences and co-authored a book chapter. Dr. Murugan holds a Ph.D. in Applied Electromagnetics from the University of Manitoba, Canada. He is an Affiliate Assistant Professor with the University of Washington EE Department, a Distinguished Lecturer for the IEEE Electronics Packaging Society (EPS), an Associate Editor for the IEEE Transactions on CPMT journal, a Senior Member of IEEE, the founder of the IEEE EPS Dallas Chapter, and the current Chair of the IEEE Dallas Section (Region 5).

Course description:

The scaling of transistors and chips has reached a point of diminishing returns, with each node becoming more complex and costly. In the “More than Moore” Era, advanced packaging technologies show promise by bridging the gap. However, these technologies challenge traditional package design verification tools and methodologies. Complex miniaturization and integration exacerbate coupled interactions with multiphysics (e.g., electrical, thermal, mechanical) and multidomain (chip-package-PCB system). Without a paradigm shift in the traditional design verification modeling approach, potential business impacts are highly likely. These impacts include costly re-spins, increased design cycle time, and time-to-market. To ensure first-pass design success, coupled multiphysics and system co-design (MSC-D) is emerging as the renewed modeling methodology.

This course covers predictive multiphysics and multiscale modeling methodologies in the design of advanced IC packaging technology. The material is delivered by leveraging the pedagogical approach of the 3W’s (Why, When, and What) to 1H (How). Whenever appropriate, the impact of predictive modeling will be demonstrated on real-world IC and package/system designs. The learning objectives are multifold — a comprehensive understanding of Multiphysics and Multiscale modeling fundamentals, selecting the optimal modeling approach based on the problem at hand, and the ability to interpret the modeling results.

Current state-of-the-art, challenges, and potential solutions will be covered.

8:30 am – 12:45 am “Advanced Packaging for MEMS and Sensors”

Course instructor: Horst Theuss

Horst Theuss received his Ph.D. degree in Physics from the University of Stuttgart, Germany in 1993. As a research staff member at the Max Planck Institute for Metal Research he concentrated on magnetic properties of superconductors and amorphous materials. Within a post-doctoral assignment at the IBM Almaden Research Center in San Jose, CA, he worked on magneto-optical properties of exchange-coupled thin layers. In 1996, he started his industrial career at Vacuumschmelze GmbH, Hanau/Germany as a product marketing manager for specialty alloys. Horst Theuss joined Infineon Technologies, Regensburg, Germany in 2000. Since then, he has been working on package concepts and processes in the fields of discrete semiconductors, wafer level packaging, cavity packaging, materials and system integration. As a Senior Principal he is today responsible for predevelopments focusing on MEMS and sensors. Over the years, Horst has continuously contributed to a variety of conferences and magazines with presentations, papers and seminars. He holds more than 100 patents and is co-editor of the “Handbook of Silicon based MEMS Materials and Technologies”.

Course description:

Sensors are everywhere! They create data and provide the “food” for the Internet of Things. Which specific requirements distinguish MEMS and sensor packaging from standard assembly? How are these challenges being tackled? Do we need advanced packaging technologies for MEMS? These are just a few questions which are addressed in the course.

MEMS involve mechanically movable or oscillating parts creating the need for cavity packaging. Concepts for cavity packages are followed by a discussion of package induced stress and its impact to MEMS performance. Among others, respective case studies comprise pressure sensors and MEMS-microphones including a discussion on MEMS-specific materials properties. The advanced packaging section contains an investigation on integrating MEMS-microphones into Fan Out Wafer Level Packages. Robustness requirements and approaches for risk mitigation in harsh environments represent further topics within the PDC’s MEMS section.
The course will go through package requirements of magnetic sensors and stress the importance of advanced packaging for GHz devices – including antenna-in-package technology. 
The concluding chapter deals with heterogeneous integration topics. Where is the overlap of the processor-driven world of advanced packaging and the MEMS/Sensor world? Where are the differences and how can we overcome them? A discussion on these topics will be welcome!

Dr. Horst Theuss
10:45 am – 12:45 am: “Chiplet Design and Heterogeneous Integration Packaging”

Course instructor: John Lau

John H Lau, with more than 40 years of R&D and manufacturing experience in semiconductor packaging, has published more than 525 peer-reviewed papers (380 are the principal investigator), 50 issued and pending US patents (30 are the principal inventor), and 23 textbooks (all are the first author). John is an elected IEEE fellow, IMAPS Fellow, and ASME Fellow and has been actively participating in industry/academy/society meetings/conferences to contribute, learn, and share.

Course description:

Chiplet is a chip design method and heterogeneous integration is a chip packaging method. Chiplet design and heterogeneous integration packaging have been generated lots of tractions lately. For the next few years, we will see more implementations of a higher level of chiplet designs and heterogeneous integration packaging, whether it is for cost, time-to-market, performance, form factor, or power consumption. In this lecture, the following topics will be covered: (1) System-on-Chip (SoC); (2) Why Chiplet Design; (3) Chiplet Design and Heterogeneous Integration Packaging (a) Chip Partition and Chip Split, (b) Chip partition and Heterogeneous Integration, (c) Chip split and Heterogeneous Integration, and (d) Advantages and Disadvantages; (4) Lateral Communication between Chiplets (e.g., Bridges) (a) Bridge Embedded in Build-up Package Substrate, (b) Bridge Embedded in Fan-Out EMC with RDLs, (c) UCIe, and (d) Hybrid Bonding Bridge; (5) Chiplet Design and Heterogeneous Integration Packaging (a) Multiple System and Heterogeneous Integration with Package Substrate (2D IC Integration), (b) Multiple System and Heterogeneous Integration with Thin Film layer on the Package Substrate (2.1D IC Integration), (c) Multiple System and Heterogeneous Integration with TSV-less (Organic) Interposer (2.3D IC Integration), (d) Multiple System and Heterogeneous Integration with Passive TSV-Interposer (2.5D IC Integration) for artificial intelligence applications, and (e) Multiple System and Heterogeneous Integration with Active TSV-Interposer (3D IC Integration); (6) Summary; (7) Trends in Chiplet Design and Heterogeneous Integration Packaging.

John-H-Lau Portrait
8:30 am – 12:45 am: “Flip Chip Fabrication and Applications“

Course instructor: Eric Perfecto

Eric Perfecto has over 41 years of experience working in the development and implementation of C4 and advanced Si packages at IBM and GlobalFoundries. Eric’s responsibilities include UBM and Pb-free solder definition for C4 and u-Pillar interconnect, and yield improvements in C4 and 3D wafer finishing. He holds a M.S. in Chemical Engineering from the University of Illinois and a M.S. in Operations Research from Union College. Eric has published over 80 papers in conferences and journals, including two best Conference Paper Awards and the 1994 Prize Paper Award from CMPT Trans. on Adv. Packaging. He holds 60 US patents and has been honored with three IBM Outstanding Technical Awards. Eric was the 57th ECTC General Chair in Reno, NV, and the Program Chair at the 55th ECTC. Eric is an IEEE Fellow, an EPS Distinguish Lecturer and EPS VP of Education.

Course description:

This course will cover the fundamentals of all aspects of flip chip fabrication and assembly technologies. It is divided into two main sections. The first part covers the main type of assembly technologies chip package interaction, package warpage control, yield detractors, substrate technologies, etc. The second dives into the depth of the fundamental aspect of flip chip fabrication mainly; interconnect technologies, under-bump metallurgy selection, fabrication methods and solder depositions methods. The course will cover the various failure modes related to bumping, such as barrier consumption, Kirkendall void formation, non-wets, BEOL dielectric cracking, etc.  Special focus of the course will be on fine pitch technologies, mainly u-Pillar and Hybrid bonding. The goal of this course is to provide the students with a better understanding of flip chip and assembly applications so that a reliable, innovative, better time to market, and more cost-effective solution can be achieved.

Course Outline
1. Introduction to Flip Chip Technologies
2. Flip Chip Technologies: Mass Reflow Process
3. Flip Chip Technologies: Thermal Compression
4. Substrate Technologies, Underfill, Package Warpage Control, and Yield
5. Flip Chip Reliability Assessment, Failure Modes, Examples, and Modeling
6. Flip Chip Si Package Co-Design
7. Chip-Package Interaction and Flip Chip Electromigration
8. Flip Chip New Trends: Wafer Level CSP; Wafer Level Fan-Out; and Panel-Level Packaging
9. Fine pitch interconnect options (for <100um pitch)
10. Bumping Ground Rules
11. Flip Chip Under-bump Metal and Intermetallic
12. Flip Chip Solder Deposition Processes
13. Cu Pillar Technology
14. Flip Chip Solder Selection and SLID
15. Hybrid Bonding (for less that 10um pitch)