ESTC 2024




Johanna M. Swan
Intel Fellow and Director of Package Research and Systems Solutions in Components Research, Technology Development, Intel Corporation

Johanna M. Swan is an Intel Fellow and the Director of Package Research and Systems Solutions in Components Research within Technology Development at Intel Corporation. She leads a multidisciplinary team of researchers charged with developing novel technologies and package architectures to enable continued semiconductor scaling, mm-wave communications at various length scales and differentiating capabilities within packaging.
An expert in advanced electronic packaging technologies, Swan began her Intel career in 2000, focusing initially on packaging solutions for wireless, cellular and memory products. She initiated Intel’s first through silicon via (TSV) die stacking program and led research in early TSV architectures. She and her team also developed a stacked-package chip-scale package (CSP) and a mixed-technology CSP. Since assuming her current role in 2006, Swan and her team have pioneered numerous innovative packaging technologies, including a multi-die interconnect silicon bridge and an associated enabling printing solution (EMIB) as well as more recent technologies such as Foveros Omni (ODI). She holds over 150 patents primarily in the field of electronic packaging. Before joining Intel, Swan spent 16 years at Lawrence Livermore National Lab (LLNL) as a Mechanical Engineer.




Electronics Integration: Challenges in Computed Tomography Scanners

Dr. Michael Hosemann
Head of Digital Electronics at Healthineers Computed Tomography Detector Center, Siemens

Dr. Michael Hosemann is the Head of Digital Electronics at Siemens Healthineers Computed Tomography Detector Center. This spans a range from front-end mixed-signal ASIC development via PCB design, firmware development for ASIC control, data processing to wireless data transmission. Michael did his Diplomingenieur and doctorate degrees at Technische Universität Dresden. Before joining Siemens Healthineers he worked for a variety of companies in Cambridge, UK and Germany, mainly designing wireless and medical systems.


Medical devices pose a large spectrum of challenges for integration of electronics components.

This talk highlights some of those challenges based on the world’s first photon-counting computed tomography scanner, Siemens Healthinneers’ Naeotom Alpha. Examples include gap-less 3D assembly of detector ASICs to handling measurement data in excess of 500Gbit/s.


Challenges and Opportunities of Semiconductor Packaging in the Chiplet Era

Dr. Yasumitsu Orii
Senior Managing Executive Officer in 3D Assembly Division, Rapidus Corporation

Dr. Yasumitsu Orii joined IBM Japan in 1986, was a pioneering figure in Flip Chip organic packages, enhancing performance and miniaturization in servers, laptops, and HDDs. With Moore’s Law limitations, packaging technology gains significance for next-gen servers. Yasumitsu led innovations such as flip chip on FPC for HDDs and developed C2 technology for low-cost flip chip bonding in consumer electronics, licensed to a Taiwanese firm. At IBM Research Tokyo, he spearheaded projects on 3D-IC and Neuromorphic Computing. After leaving IBM in 2014, he joined NAGASE & CO., LTD., launching material informatics software as a service. He left NAGASE and in December 2022 and joined Rapidus Corporation, where he now serves as Senior Managing Executive Officer in the 3D Assembly Division.



Splitting a System-on-Chip (SoC) chip into individual chips (chiplets) by function brings improved yields, shorter design, development cycles, and cost reduction. However, moving from monolithic chips to chiplets brings forth new challenges in high-density interconnects, thermal management, and testing. Additionally, the packaging structures are becoming more complex, resulting in increased design complexity. To address these challenges, the entire industry should promote the integration of front-end and back-end processes and establish a chiplet ecosystem.


Packaging: then, now and in the future.

Subramanian S. Iyer
Director National Advanced Packaging Manufacturing Program, CHIPS R&D Office, National Institute of Standards and Technology, Department of Commerce. Los Angeles CA.

Subramanian S. Iyer (Subu) is the Director of the National Advanced Packaging Manufacturing Program (NAPMP) and a Distinguished Professor at UCLA, holding the Charles P. Reames Endowed Chair in Electrical Engineering. He’s affiliated with the Materials Science and Engineering Department. Previously, he served as an IBM Fellow. His pioneering work includes the development of significant technologies such as SiGe base HBT, Salicide, and embedded DRAM. He has led advancements in packaging and device innovations, exploring possibilities for wafer-scale architectures and medical engineering applications. His awards, including the IEEE Daniel Noble Medal and the iMAPS Daniel C. Hughes Jr Memorial Award.

List of publications/patents:


Packaging has evolved from the role of primarily protecting the chip to one of overall system integration of heterogeneous chiplets. An important aspect of this integration is miniaturization. Feature sizes such as substrate wiring pitch, die-to-substrate bonding pitch, and inter-die distances need to shrink in a predictable manner to approach monolithic wiring pitches, last level via pitches and IP block spacings. We refer to this as shrinking down of the package. Simultaneously, we need to increase the number of dies interconnected on the package to improve performance and functionality. We refer to this as scaling out of the package.  Current approaches to this include additional levels in the packaging hierarchy with concomitant increases in complexity and cost. We need to think of new ways of flattening the packaging hierarchy by enabling substrates with finer wiring pitches and the ability to assemble dies at fine pitch at high throughput. Besides the technology and processes needed to accomplish this, there are other difficult issues that need to be addressed: these include power delivery and thermal dissipation, high bandwidth, and potentially active wired, wireless, and photonic connectors to the external world or between subsystems. Finally, to make this vision a reality a chiplet eco system needs to be developed with mechanical and electrical standards that ensure interoperability and a high level of reuse. Similarly, a comprehensive EDA approach needs to be developed that goes well beyond electrical abstraction of the system and includes among other things thermal, thermomechanical considerations, power delivery, test methodology and reliability.  This is a challenging opportunity and promises to continue the trend set by Moore’s law, for system integration.