IQM Quantum Computers

Presenter: Olli-Pentti Saira, Head of Emerging Technologies

Title: Advanced Quantum Device Packaging at IQM towards Million Qubits

Abstract:

Quantum computers consist of a coherent core and a classical (non-quantum) control system. In IQM’s implementation, the coherent subsystem consists of non-linear microwave resonators, realized with superconducting thin films and cooled to an operating temperature of about 20 mK. IQM’s advanced packaging research studies the technologies for connecting the coherent on-die elements to off-die electrical control interfaces. This talk explores the cross-disciplinary challenges arising from quantum device physics and the cryogenic operation environment, versus the process capabilities of superconducting wafer lines and 3D integration. Our end goal is to support the deployment of million-qubit error corrected machines in the early 2030’s.

IMEC

Presenter: Clément Godfrin, Device Engineer

Title: 300 mm Process Development and Technology De-Risking for Silicon Quantum Dot Spin Qubit

Abstract:

IMEC’s 300 mm process line combines state-of-the-art industrial manufacturing tools with the flexibility needed to address the challenges of large-scale spin-qubit technologies. Our work focuses on optimizing processes to realize low-disorder, low-noise quantum dots in MOS and Si/SiGe platforms, while evaluating the capabilities and limitations of lithography technologies for scalable quantum computing. In this presentation, I will describe IMEC’s device optimization strategy and process flows, highlight recent device results, and discuss a scalable architecture enabled by advanced EUV lithography for silicon spin-qubit systems. This architecture provides a pathway toward addressing scaling challenges of silicon quantum dot spin qubits systems.

Infineon

Presenter: Jochen Braumüller, Lead – Superconducting Circuits

Title: Quantum Computing Efforts at Infineon

Abstract:

In this presentation I will provide an overview on the ongoing quantum computing efforts at Infineon, with a focus on superconducting circuits. I will show Infineon’s TWPA prototype performance and provide an outlook on the superconducting circuits roadmap. Finally, I will summarize all of Infineon’s hardware approaches to quantum computing, additionally including ion traps and silicon quantum dots.

SemiQon

Presenter: Nikolai Yurttagül, Lead – Silicon Device Engineering

Title: Cryo-optimised CMOS and cryogenic packaging for Quantum Integrated Circuits

Scaling up solid-state quantum processors will require both high-efficiency cryogenic CMOS electronics for the qubit control and advanced 3D integration to enable dense interconnects between qubits and their control circuitry. We manufacture fully depleted silicon-on-insulator circuits with ultralow-temperature-adjusted switching characteristics on a cryo-CMOS pilot line. Using this technology, individual MOSFETs consistently achieve record-low subthreshold swings in the range of 0.3-2 mV/dec at sub-Kelvin temperatures, enabling substantial reductions in supply voltage and, consequently, power dissipation to levels compatible with the cooling power figures of millikelvin refrigerators. This low-power cryo-optimised CMOS platform forms the foundation for fully packaged 2.5D/3D integrated quantum-control systems, enabling scalable co-integration of qubits, control electronics, RF routing, and signal distribution within a compact cryogenic environment, providing a key technological pathway towards large-scale quantum processors.

One of the key factors for establishing and successfully sustaining the semiconductor and packaging industry in Europe is the availability of highly skilled professionals and engineers. Although the labor market—particularly in the high-tech sector—is just as global as the market for goods, concerted efforts to ensure excellent university and vocational training opportunities in Europe are essential.

The presentations in this session examine the prevailing conditions and highlight specific initiatives in this field. A discussion about this and other possibilities is highly welcome.

Guoqi Zhang, Prof., Delft University of Technology, The Netherlands

Title: Workforce Development – the Key Success Factor for European’s backend industry

Abstract: Heterogenous system integration and packaging have always been essential part of global semiconductor value chain. However, they were not considered as technologically challenging and scientifically exciting as the frontend technology. Today, with the semiconductors in transition toward system optimization, the critical bottleneck is shifting from transistor scaling only to heterogeneous system integration, and the semiconductor system architecture is in redefinition. This talk will highlight some observations of “PACK4EU” project, especially on the workforce development, and SWOT analysis and possible solutions will be discussed.

Matti Mäntysalo and Heikki Holmberg, Tampere University, Okmetic, Finland

Title: Workforce Constraints in Microelectronics: Beyond the Talent Gap Narrative

Abstract: Europe’s microelectronics ambitions are increasingly constrained by workforce availability. Using Finland as a case study, this presentation shows that the challenge is not only a shortage of graduates, but a structural misalignment between education and industry needs. Current education pipelines are insufficient to meet projected demand, while demographic trends and talent mobility further limit workforce availability. In addition, evidence from European studies indicates that skill requirements are evolving, with increasing demand for interdisciplinary competencies and new roles across the semiconductor value chain. Existing degree structures often adapt slowly to these changes. We therefore argue that the “talent gap” should be reframed as a system-level problem, requiring coordinated action across education, industry, and policy. Without such changes, workforce limitations risk becoming a major bottleneck for Europe’s semiconductor growth and competitiveness.

Krzysztof Nieweglowski, PhD, TUD Dresden University of Technology, Germany

Title: Teaching of Advanced Technology on Electronics and Photonics in Higher Education using Digital Additive Manufacturing and 3D Printing Techniques – Highlights of EU Erasmus+ Cooperation Partnerships Project TADAM3D-µP

Abstract: The presentation shows new educational pathway for international teaching and learning on advanced engineering technologies in the field of electronics and photonics explored in the EU Erasmus+ Cooperation Partnerships Project TADAM3D-µP. This collaborative project involves three European universities: Wrocław University of Science and Technology (WUST), University of Žilina (UNIZA) and Dresden University of Technology (TUD) and investigates integration of three-dimensional printing (3DP) and additive manufacturing (AM) hands-on activities into university education in the Electrical Engineering field to foster students’ skills in advanced and sustainable fabrication technologies.

Prof. Thomas Zerna, TUD Dresden University of Technology, Germany

Title: STIPT – Semiconductor Talent Incubation Program Taiwan

Abstract: The early recruitment of highly qualified professionals constitutes a key competitive factor —particularly within the high-tech sector— and serves as the foundation for the smooth launch of new production facilities. Drawing on the example of a collaboration between TU Dresden and the semiconductor manufacturer TSMC, this presentation demonstrates how the company is laying intensive groundwork for its investment in Saxony, Germany, including in the realm of human resources, from a very early stage.

Panelists:

1. Eric Fribourg-Blanc, Senior Programme Officer, Chips JU
2. Dirk Schumann, Director APECS Pilotline, FMD / represented by Erik Jung, Head of APECS Chiplet Integration 2.5D & 3D, Fraunhofer IZM
3. Jean-Charles Souriau, Scientific Leader on Heterogeneous Integration & Wafer Level Packaging, CEA-Leti
4. Andy Miller, Director, Advanced Packaging Technology Development, imec
5. Peter O’Brien, Head of Research Group, Director of Photonics Packaging Pilot Line, Tyndall National Institute
6. Tuomas Lahtinen, Director, SiPFAB, Tampere University

Representing:

1. Chips JU – The primary financial and operational manager for the Chips for Europe Initiative’s Advanced Pilot Lines.
2. APECS – Advanced packaging
3. FAMES – Fully depleted silicon-on-insulator applications
4. NanoIC – Beyond 2nm leading-edge system-on-chip
5. PIXEurope – Advanced photonic integrated circuits
6. WBG – Wide band gap materials

Abstract:

The Chips for Europe Initiative has successfully launched its first five Advanced Pilot Lines into operational reality, backed by over €3.7 billion in combined European and national funding. Financially and operationally supervised and monitored by the Chips Joint Undertaking (Chips JU), these open-access facilities are supposed to bridge the gap between lab research and industrial manufacturing by letting companies test and prototype next-generation microelectronics. The focus of the short presentations per Pilot Line followed by an intense Panel Discussion will be on Advanced Packaging / System Integration topics – following the scope of the conference – today’s status, industry perception and acceptance, first achievements, the collaboration between the Pilot Lines in terms of Advanced Packaging / System Integration, and the plans for the next 12 month.

The field of microelectronics/photonics packaging and advanced packaging is crucial for the future of electronic components and systems. Independently, if we consider mobile phones, data centers, automobiles or healthcare equipment, all these applications strongly depend on electronic systems. Microelectronics packaging and advanced packaging are the cornerstone of innovation in all industry segments. As new packaging technologies, materials, and processes emerge, a skilled workforce is required to push further technological advancements.

This competition invites students to work on a realistic reliability engineering problem inspired by automotive electronics. Participants will analyze how thermal expansion mismatch between package and PCB can drive damage accumulation in BGA solder joints and will propose an improvement strategy grounded in simulation results.

Speakers:

1. Yik Yee (YY) Tan Ph.D., Principal Technology & Market Analyst, Semiconductor Packaging & Assembly, Yole Group
2. Markus Leitgeb, Director Research & Development, Microelectronics Packaging, AT & S Austria Technologie & Systemtechnik Aktiengesellschaft
3. Habib Hichri, Executive Vice President and Senior Fellow for Global Applications and Business Development, Ajinomoto Fine-Techno USA
4. Peter O’Brien Ph.D, Head of Research Group, Director of Photonics Packaging Pilot Line, Tyndall National Institute

Abstract:

AI is demanding high density, thermally manageable robust and cost-efficient packaging. Substrate technologies are critical to delivering these solutions. They enable the use of high-density Heterogeneous Integration to drive better electrical, memory and power performance, while also managing the mechanical and thermal stresses that the high thermal load requirements of AI imposes.

This session will explore the emerging trends in substrate technologies evolution, including materials developments and the move to co-packaged optics. It will also highlight the challenges that need to be considered by the packaging ecosystem to support high yielding substrate fabrication, assembly and systems integration.