ESTC 2020 schedules some Special Sessions.
Hot topics in the field of electronic packaging are presented and discussed. Share your experiences and opinions with colleagues.
Rao R. Tummala, Georgia Institute of Technology, USA
Moore’s law has been the driving engine for science, technology, manufacturing, hardware, software, systems and applications, contributing to the prosperity of thousands of individuals, 100s corporations and dozens of countries. As Moore’s Law begins to come to an end, for not only fundamental reasons but also for computing performance , power, cost and investments., it is becoming clear that a different path for electronics systems must emerge. So, while transistor integration on individual 2D ICs was the basis of Moore’s Law for ICs, transistor integration can be extended in 2.5D and 3D by means of interconnections or I/Os s in the short term. This is referred to as Moore’s Law for Packaging. Just like Moore’s Law has both doubling of transistors and simultaneous cost reduction from node to node every 18-24 months, Moore’s Law for system interconnections can do the same. Interconnections have been driven by computing systems and within computing systems, between logic and memory .The new era of artificial intelligence mimicking human brain with several orders better computer performance is yet another reason for the end of Moore’s Law . Human brain is the ultimate systems packaging for highest performance in smallest size with lowest power. Human brain is the new packaging density and efficiency standard that may have to be viewed as more than current 3D architectures. A typical human brain has about 90 billion nerve cells interconnected by trillions of synapses providing trillions of pathways for brain to process info. Moore’s Law for Packaging , therefore must duplicate this architecture.
The packaging or I/Os has historically evolved from DIPs in 1970s with 16 I’Os, QFP in 1980s with 64 I/Os, ceramic packages in 1990s with more than 500 I/Os, laminate packages in excess of 1000 and silicon packages approaching 16,000.Artificial intelligence mimicking human brain may need several orders of magnitude.
Currently, the best Moore’s Law for packaging is with wafer-based silicon packaging . But silicon- based packaging has many limitations at material, device, circuitry and system levels.
The talk describes a roadmap from Moore’s Law for ICs to Moore’s law for electronic and photonic interconnections and eventually to quantum computing.
Prof. Rao Tummala is a Distinguished and Endowed Chair Professor Emeritus at Georgia Tech in USA. He is well known as an industrial technologist, technology pioneer, and educator. Prior to joining Georgia Tech, he was an IBM Fellow, pioneering such major technologies as the industry’s first plasma display and industry’ first 100- chip MCM with leading-edge RDL, flipchip and liquid cooling, now called 2.5D. He is the father of LTCC and System-on-Package(SOP) technologies. As an educator, Prof. Tummala was instrumental in setting up the largest Academic Center in System-On-Package vision for Electronic Systems funded by NSF as the first and only NSF Engineering Research Center in US in Packaging at Georgia Tech.The Center with its integrated approach to research, education and industry collaborations produced more than 1500 engineers and collaborated with more than 200 companies in US, Europe, Japan, Korea, Taiwan and China. He received many industry, Academic and Professional Society awards including Distinguished Alumni of Illinois, Indian Institute of Science and the highest Faculty award from Georgia Tech—The Distinguished Faculty. He has published 800 technical papers and invented many technologies that resulted in over 100 patents. He wrote the first modern textbook in packaging, Microelectronics Packaging Handbook(1988); wrote the 1st undergrade textbook, Fundamentals of Microsystem Packaging(2001); and the 1st book introducing the concept of SOP, Introduction to System-on-Package( 2006). He was Past President OF IEEE CPMT and IMAPS. He is an IEEE Fellow and member of National Academy of Engineering in US.
Bodil Holst, Department of Physics and Technology, University of Bergen, Norway
The ability to pattern materials at ever-smaller sizes using photolithography is driving advances in nanotechnology and electronics, with extreme ultraviolet lithography being the current state-of-the-art. However, the secondary electron blur from the high energy extreme-ultraviolet photons hinders the creation of single molecule (1 nm) patterns. The EU-funded Nanolace project (start up 1 January 2020) aims to demonstrate a breakthrough nanolithography technique: Mask-based atom lithography, which enables fast patterning of arbitrary patterns with nm resolution.
Professor Bodil Holst is a professor of Nanophysics at the University of Bergen. She holds a Ph.D in experimental physics from the University of Cambridge. Bodil Holst research fields ranges from atom optics: lithography and microscopy over nanostructured surfaces to archaeology. In 2019 she was appointed chair of the Kavli Prize committee in Nanoscience.
Organized by William Chen, ASE Group, USA
Heterogeneous Integration Roadmap (HIR)
Workshop @ ESTC 2020
September 14th 2020
9:00 am – 11:50 am
Live On-Line Workshop
The Heterogeneous Integration Roadmap (HIR), released October 2019, is a roadmap to the future of electronics identifying technology requirements and potential solutions. The primary objective is to stimulate pre-competitive collaboration between industry, academia and government to accelerate progress. The roadmap offers professionals, industry, academia and research institutes a comprehensive, strategic forecast of technology over the next 15 years. The HIR also delivers a 25-year projection for heterogeneous integration of Emerging Research Devices and Emerging Research Materials with longer research-and-development timelines.
This HIR workshop @ESTC will feature selected topics from the HIR chapters including an overview presentation. The purposes for the HIR workshop at ESTC are to feature interest & stimulate collaboration for the HIR stakeholders in Europe and the global regions.
|9:00 am - 9:05 am||Welcome|
|9:05 am – 9:30 am||HIR Overview|
|9:30 am – 10:50 am||HIR Chapters Highlight Session|
|Session Moderators: Rolf Aschenbrenner & Bill Chen|
|9:30 am – 9:40 am||SiP & Module|
|9:40 am – 9:50 am||Integrated Photonics|
|9:50 am – 10:00 am||Automotive Electronics|
|10:00 am – 10:10 am||MEMS & Sensor Integration|
|10:10 am – 10 :20 am||Co-Design & Simulation|
|10:20 am – 10 30 am||5G|
|10 :30 am – 10 50 am||Live Q&A (20 Minutes) Moderators direct Q&A flow|
|10:50 am – 11: 50 am||Live Panel Session|
Theme: Technology Roadmap: Visionary Tool for Accelerating Innovation
Moderators : Bill Bottoms & Hubert Lakner