ESTC 2018 schedules some Special Workshops on Wednesday afternoon, September 19th.
Hot topics in the field of electronic packaging are presented and discussed. Share your experiences and opinions with colleagues.
Access to those Special Workshops is included in the conference fee.
Workshop A - Heterogeneous Integration Roadmap
Our Industry has reinvented itself through multiple disruptive changes in technologies, products and markets. With the rapid migration of logic, memory and applications to the Cloud infrastructures, Data Centers and 5G Networks, the Internet of Things (IoT) to Internet of Everything (IoE), Autonomous Vehicles, the proliferation of Smart Devices every where, and increasing interest in 5G, artificial intelligence (AI) & Virtual Reality (VR), the pace of innovation is increasing to meet these challenges. What are the paths forward?
The IEEE Heterogeneous Integration Technology Roadmap (HIR), is sponsored by the IEEE Electronic Packaging Society (EPS), the Electron Devices Society (EDS), Photonics Society together with ASME EPPD and SEMI. It will address the future directions of heterogeneous integration technologies and applications serving future markets and applications, so very crucial to our profession, our industries, academic and research communities. Following the spirit of ITRS, the HIR is a pre-competitive technology roadmap provides long-term vision to identify the needs of future technology challenges, roadblocks, and potential solutions focused on system integration and broad market applications in order to accelerate progress for the broad electronics industry.
|Welcome Messages||Hubert Lakner (Fraunhofer IPMS) & Karlheinz Bock (TU Dresden)|
|Heterogeneous Integration Roadmap Overview||Bill Chen (ASE) & Bill Bottoms (Third Millenium Test Solutions)|
|Opportunities & Challenges in Automotive Electronics Packaging||Andreas Middendorf (Fraunhofer IZM|
|Photonics Integration||Gunnar Böttger (Fraunhofer IZM)|
|ITRW & Power Electronics Integration||Pete Wilson (University of Bath) & Jing Zhang (Heraeus Electronics)|
|Heterogeneous Integration Roadmap TWG Panel||Panel Co - Moderators: Jean Trewhella (GLOBALFOUNDRIES) & Klaus Pressel (Infineon technologies)|
|System-in-Package (SIP)||Rolf Aschenbrenner (Fraunhofer IZM)|
|WLP & Fanout||John Hunt (ASE)|
|Co-Design & Simulations||Chris Bailey (University of Greenwich)|
|5G & Analog & Mixed Signal||(to be confirmed)|
|Panel (all speakers ) Q&A Session|
|Wrap-Up||Bill Bottoms & Bill Chen|
Workshop B - Fan-Out Panel: Is the Industry Ready?
Fan-out wafer-level packaging (FO-WLP) technologies have been developed across the industry over the past 15 years and have been in high volume manufacturing for over 8 years. FO-WLP has matured enough that it has come to a crossroads where it has the potential to change the electronic packaging industry by eliminating wire bond and bump interconnections, substrates, leadframes, and the traditional flip-chip or wire bond chip attach and underfill assembly technologies across multiple applications. The next step is economy of scale: the conversion from 300mm to panel! Panel Fan-Out has been an exciting topic for in the US and Asia for over 3 years and we are bringing that excitement to IEEE Electronics Package Society’s Electronic System-Integration Technology Conference (ESTC). Panelists representing consortia, OSATs, materials suppliers, and market data research will all speak about how their company or consortium is addressing (or not addressing) the panel fan-out market and discuss the intersection with European markets such as automotive, IoT, and flexible electronics. There will also be time to take questions from the audience.
BETH KESER, Ph.D., a recognized global leader in the semiconductor packaging industry with over 20 years of experience, received her B.S. degree in Materials Science and Engineering from Cornell University and her Ph.D. from the University of Illinois at Urbana-Champaign. Beth’s excellence in developing revolutionary electronic packages for semiconductor devices has resulted in 27 patents and patents pending and over 40 publications in the semiconductor industry. Based in Munich, Germany, Beth is Director if the Components and Systems Solutions Department at Intel Corporation in the Communication Devices Group.
TANJA BRAUN studied mechanical engineering at Technical University of Berlin and joined Fraunhofer IZM in 1999. Since 2000 she is working with the group Assembly & Encapsulation Technologies and since 2016 she is head of this group. In 2013 she received her doctorate degree from the Technical University of Berlin for the work focusing on humidity diffusion through particle-filled epoxy resins. Her recent research is focused on wafer and panel level packaging technologies and Tanja is leading the Fan-out Panel Level Packaging Consortium at Fraunhofer IZM Berlin. Tanja Braun holds also several patents in the field of advanced packaging. In 2014 she received the Fraunhofer IZM research award.
JAN KELLAR joined Deca Technologies in 2010 where she is responsible for advanced wafer level package design including M-Series fan-out design using Adaptive Patterning™ dynamic lithography technology. Jan has over 25 years of experience working in the semiconductor industry specializing in Advanced Package Design. Prior to joining Deca Technologies, Ms. Kellar was Global IC Package Design Manager at Motorola and Freescale Semiconductor.
JAN VARDAMAN is president and founder of TechSearch International, Inc., which has provided market research and technology trend analysis in semiconductor packaging since 1987. She is the co-author of How to Make IC Packages, a columnist with Printed Circuit Design & Fab/Circuits Assembly, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She is a senior member of IEEE EPS and is an IEEE EPS Distinguished Lecturer. She is a member of SEMI, IMAPS, and MEPTEC. She received the IMAPS GBC Partnership award in 2012. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium.
MARION WEIGAND studied Chemical Engineering at the University of Applied Sciences in Darmstadt and jointed DuPont in 1987. She spent her 31 years with DuPont in the Electronic Materials business unit, mainly in the semiconductor materials group. In 1997 she was part of the foundation of Hitachi Chemical DuPont MicroSystems (HDMS), a Joint Venture between Hitachi Chemical and DuPont Electronics. Since 2000 she is Managing Director of the European HDMS legal entity with Technical Service and Sales Management experience in Europe and the USA for the HDMS product portfolio of liquid polymer coatings for various semiconductor applications. Additionally, Marion serves as the Chairperson of the Board of Directors & Country Leader of DuPont in Germany.
Workshop C - Challenges for Advanced Packaging in the Dawn of Autonomous Driving
This panel discussion focuses on the challenges for advanced packaging in the era of ADAS and the dawn of autonomous driving. Package choice, design, and materials impact the performance of Advanced Driver Assistance Systems (ADAS) sensors and the sensor fusion processors used to analyze sensor input. Fan-out wafer level packages (FO-WLPs) are used for automotive radar, but the package designs differ from those found in smartphones. What are the different design considerations for packages used in automotive vs. consumer, computing, and telecom? How important is co-design? Many sensor fusion processors are packaged in flip chip-plastic ball grid arrays (FC-PBGAs), but the materials used to fabricate the substrates differ from packages used for other applications. What failure modes are being observed? What reliability standards should be followed in qualifying packages for ADAS and autonomous driving? Does the industry need to meet Grade 0? Power dissipation requires thermal materials and solutions that can meet automotive reliability specifications. Are current material sets adequate? Are new materials needed and what are the requirements for these materials? A set of experts will address these issues and others in a dynamic discussion setting.
The panel moderator will be E. JAN VARDAMAN, President and Founder of TechSearch International, Inc. Companies involved in IC and package design, material development, assembly, and testing will find the session enlightening. The discussion will be useful for individuals involved in package development and supply chain management. Executives, business managers, and engineers will have the opportunity to ask questions to the panel.
KARLHEINZ BOCK studied electronics and communication engineering at the University of Saarbrücken, Germany. In 1994 he achieved the Dr.-Ing. degree in RF microelectronics from the University of Darmstadt, Germany. Since January 2001 until September 2014 he has been with the Fraunhofer Institute for Reliability and Microintegration IZM in Munich (since 2010 renamed Fraunhofer Research Institution for Modular Solid State Technologies EMFT), Germany, as head of the Polytronic and Multi-Functional Systems department. Since March 2008 until September 2014 he also served as professor of Polytronic Microsystems at the University of Berlin (TU Berlin). He received in 2012 the Dr. honoris causa from Polytechnical University of Bukarest in Romania for his contributions to develop Polytronics (large area flexible heterogeneous systems). Since October 2014 he serves as professor of Electronics Packaging and director of the Institute for Electronic Packaging Technology (IAVT) at the TU Dresden (University of Dresden). He contributed in more than 290 publications, 25 patents, 10 book chapters and 70 invited talks.
THORSTEN MEYER is Principal Engineer Package Concept Engineering at Infineon Technologies in Regensburg, Germany, responsible for New Package Platforms and New Package Definition. Until March 2015 he was leading the Package Technology and Innovation department at Intel Mobile Communications (IMC) in Regensburg. Prior joining IMC, he was overall project leader for the development of Wafer Level Packaging Technologies at Infineon in Regensburg and earlier in Dresden. Thorsten Meyer is author of multiple publications and holds more than 140 patents and patent applications in the area of advanced packaging.
JEAN-MARC YANNOU started his career as a Test & Product Engineer at Texas Instruments, first in France then in the USA. He then joined Philips Semiconductors (now NXP) as principal engineer where he managed the company’s initiatives in System-in-Package technologies. Next, he became a senior consultant and market analyst on advanced semiconductor packaging technology for Yole Développement, a market research consultancy. Along with his professional activities, Jean-Marc served as chairman of the France chapter of IMAPS (International Microelectronics and Packaging Society) from 2010 to 2014. Jean-Marc joined ASE Group in 2012 where he serves as a Technical Director for Europe.
Workshop D - EuroPAT-MASIP - Recent advantages in electronics packaging
EuroPAT-MASIP, ECSEL JU project, strives to increase the competitiveness and the global market share of the European semiconductor industry by fostering the competence and capabilities of semiconductor packaging. The three-year project’s total budget is about 30 M€, with roughly half of it from ECSEL and national funding. Coordinated by Amkor technologies, Steffen Kröhnert, partners from nine European countries cover the semiconductor packaging, assembly and test value chain all the way from foundry, packaging, component tests to system tests till the end user. Project website:www.europat-masip.eu.
Focusing on fan-out wafer level packaging (FO-WLP), the project develops packages for six pilot products: WLAN front-end IC (NXP France), silicon photomultiplier (KETEK), automotive inertial sensor (Murata), next-generation WL camera (Valeo), 60 GHz radar sensor (InnoSenT) and a car tyre sensor (Nokian Tyres). In addition, the project develops a wide portfolio of technological building blocks for integration concepts. These include modelling and simulation, 3D MtM and SiP, packaging technologies, materials as well as test strategy and methods. The new equipment include e.g. plasma dicing technology.
The session highlights the key results achieved during the first 18 months:
- HEIKKI KUISMA (Murata): An automotive combined inertial sensor in FO-WLP packaging technology with description of the design considerations, performance and reliability test results and failure analysis.
- THOMAS UHRMANN (EV Group): Laser Debonding enabling ultra-thin Fan-Out WLP devices
- GHANSHYAM GADHIYA (Faunhofer ENAS): Automated Virtual Prototyping for Fastest Time-to-Market of New System in Package Solutions
- ANDRE CLAUSNER (Fraunhofer IKTS): Advanced Process and Materials Characterization at the Micro- and Nanoscale
- CHRISTOPHER JOHNSTON (Plasma-Therm): Defect-Free Dicing for Higher Device Reliability
HEIKKI KUISMA graduated from the Helsinki University of Technology (now Aalto University) in 1978 with MS degree, electron physics as the major topic. Having worked in VTT, Vaisala Oy and VTI Technologies Oy (now Murata Electronics) he has over 40 years of experience in MEMS technologies and devices including all aspects of the device: MEMS, circuits and packaging. He was a long term Director of Advanced Development in VTI and Murata and is now partially retired but still working as Program Manager for development of selected advanced technologies. He has been a WP leader in many multi-party publicly funded projects. He is an author of tens of patent publications.
THOMAS UHRMANN is director of business development at EV Group (EVG) where he is responsible for overseeing all aspects of EVG’s worldwide business development. Specifically, he is focused on 3D integration, MEMS, LEDs and a number of emerging markets.
Prior to this role, Uhrmann was business development manager for 3D and Advanced Packaging as well as Compound Semiconductors and Si-based Power Devices at EV Group. He holds an engineering degree in mechatronics from the University of Applied Sciences in Regensburg and a PhD in semiconductor physics from Vienna University of Technology.
GHANSHYAM GADHIYA received his M.Sc. degree in Micro and nano systems, with a specialization in Finite element analysis of power module from Technical university of Chemnitz in 2013. Since 2014, he is working as a scientific researcher at the Micro materials center, Fraunhofer ENAS. His main research focus includes parametric finite element modelling, thermo-mechanical simulation and optimization of microelectronics packages using FE analysis. He has been also involved with several industrial projects for residual stress, humidity and vibrational analysis. His current research interests include fan-out wafer level packaging technologies based system-in-package and micro-electronics failure analysis.
ANDRE CLAUSNER finished his Diplomingenieur degree in applied mechanics in 2007 and joined afterwards the International Research Training Group „Materials and Concepts for Advanced Interconnects” working in the field of advanced materials for microelectronics until 2010. He joined Fraunhofer IKTS in 2013 after completing his dissertation at the Technical University Chemnitz in physics, focusing on the area of nanoindentation. The goal of his doctoral work was the evaluation of nanoindentation methods for the determination of yield stresses in various classes of materials. He brings with him a vast knowledge in the field of mechanical materials behaviour and characterisation methods.
CHRISTOPHER JOHNSTON is the business development manager for advanced packaging at Plasma-Therm. Christopher comes to Plasma-Therm from Intel Corporation, where he served 16 years in semiconductor Fab high volume manufacturing and assembly R&D. During his last 8 years at Intel, he was the dicing equipment development and supply chain engineer. Christopher dicing technology contributions include the leading wafer laser scribing solution advanced nodes (<10nm) and the most affordable plasma dicing-on-tape solution for small and thin devices. Christopher received a BS degree in Electronics Engineering from DeVry University, MBA and MPM from Keller. Recent publications include “Plasma dicing methods for thin wafers”, Chip Scale Review (May-June 2016) and “Plasma Dicing for MEMS”, MEPTEC Report (Fall 2016).