• 2006, Dresden, Fireworks artist during welcome reception
  • 2006, Dresden, Keynote presentation
  • 2010, Greenwich, University Campus
  • 2016, Grenoble, Networking during break
  • 2014, Helsinki, Audience
  • 2016, Grenoble, Audience
  • 2016, Grenoble, Poster Presentation
  • 2008, Greenwich, Exhibition
  • 2008, Greenwich, Conference attendees
  • 2010, Berlin, Keynote
  • 2010, Berlin, Networking
  • 2014, Helsinki, Finlandia Hall

Professional Development Courses

ESTC 2018 offers high-level Professional Development Courses on Tuesday, September 18th, in the morning. Don't miss this excellent opportunity to benefit from the knowledge of international electronic packaging expert.

PDC fee

Attending a PDC is possible for an additional fee of 250 EUR (registering before early bird deadline, July 31st) respectively 300 EUR (registering after early bird deadline).

This fee includes course materials, coffee break and lunch after the PDC.

Please select the course you are interested in during your regular conference registration.

PDC 1 - Robust Electronics for Autonomous Driving


Course Outline:

  1. Electronics Packages for External Sensing and e-Drive
  2. Robustness Validation of Automotive Electronics
  3. Damage Mechanism in Automotive Electronics
  4. Q&A

The amount of electronics in vehicles has increased dramatically over the last years and will increase further in the future. Autonomous driving demands highly robust surround-sensing of the entire car for adaptive cruise control, traffic sign recognition, pedestrian detection, drowsiness detection, collision mitigation, blind spot detection, cross-traffic alert, parking assist and lane departure prevention, using a combination of many technologies that include:

  • Video cameras (mono, stereo cameras; infrared cameras for night vision),
  • RADAR (long and short range radars)
  • LIDAR (light detecting and ranging by laser light) and
  • Ultrasound sensors.

The demand for alternative, more energy-efficient forms of mobility stimulates the application of electro mobility. Electric vehicles require efficient and lighter components such as electric motors, inverters, converters, control and driver electronics and high-voltage batteries.
Electronics modules integrated in sensors and actuators facing harsh environment and higher temperatures. Smaller packages and higher integration levels are needed through embedded systems in package, multi-die packages and finer pitch packages. New packaging technologies have to be qualified for the reliability and safety automotive standards.
E-mobility increases the today's life time requirements of automotive electronics. Additional to the driving time the charging operations have to be considered. To meet this new life time requirements the qualification of electronics module is changing from the detection of defects to the study of the failure mechanisms. The robustness validation is an approach to qualification and validation based on failure mechanisms relates to specific mission profiles. Fraunhofer IMWS is a long term partner of automotive industry in failure analysis and mechanical testing and modeling. The special high resolution analysis tools and their performance will be introduced. Based on broad practical experience along complete supply chain examples of robustness validation will be demonstrated.


MERVI PAULASTO-KRÖCKEL is a professor at Aalto University School of Electrical Engineering in Finland. She completed her D.Sc at Helsinki University of Technology in 1995. Prior to joining Aalto University end of 2008, she worked over 12 years in the semiconductor industry in various R&D and management positions. Her group Electronics Integration and Reliability focuses on advanced materials and interconnect technologies for MEMS/NEMS and power electronics, as well as multi-material assemblies behaviour under different loads and their characteristic failure mechanisms. Prof. Paulasto-Kröckel has over 100 international publications in fields of microelectronics packaging and interfacial compatibility of dissimilar materials. She is Distinguished Lecturer of IEEE EPS.

MATTHIAS PETZOLD, Fraunhofer IMWS, graduated from Martin-Luther-University Halle-Wittenberg, Germany in Physics and received his PhD in 1987. After working at Halle University and for a ceramics company, he moved to the newly founded Fraunhofer institute Halle in 1991. Matthias Petzold is currently heading the institute's Center for Applied Microstructure Diagnostics (CAM) and is deputy director of the Fraunhofer Institute for Microstructure of Materials and Systems IMWS in Halle, Germany. His scientific activities include research on physical failure analysis and material diagnostics in electronics components with particular focus on quality and reliability issues in automotive applications. He is member of the steering committee of the European Symposium on Reliability of Electron Devices, Failure Physics and Analysis.

KLAUS WOLTER, TU Dresden. His research interests have embraced many aspects of microelectronics packaging, including substrate technologies, assembly technologies, photonic packaging, MEMS, joining technologies, reliability of electronic packages, and non-destructive test methods. He is well known as co-author of six textbooks, co-editor of three book series with a total of 39 books, author and co-author of more than 200 papers. He is a senior member of IEEE-CPMT. Prof. Wolter was the Director of the Electronic Packaging Lab at TU Dresden from 2003 to 2014. From March 2015 to March 2017, he was a visiting professor at the 3D Systems Packaging Research Center of Georgia Tech Atlanta where he researched on system-integration for advanced automotive electronics. Currently he is a senior professor at TU Dresden.

PDC 2 - Introduction into Photonic Packaging and Interconnection technology


The photonic Packaging and Interconnection technology (PAVT) is the interface between the optical communications engineering and classical electrical connection technology and microsystem technology. The techniques such as bonding, adhesive bonding, soldering, thick film / thin film technology and the multi-layer printed circuit board technology also be used to build up of an optoelectronic device (OEIC), such as some techniques of microsystems technology such as etching of silicon substrates or masks and coating techniques. The application of the OEICs in the communication system determines the system structure of the package that needs to be very cost effective in extreme cases, e.g. to be used in future optical Ethernet connections. This can be very expensive and time-consuming, if only some specific functions are used in a wide-area range, as has already been explained in the previous chapter to the optical transmission systems.
For clarity and definition of the roles of the photonic assembly and interconnection technology (PAVT)  a proper definition is to be introduced at this point:
"The photonic assembly and interconnection technology is used to connect optical and electrical transmission media and electrical supply lines to photonic devices in a stable, environmentally adapted housing."
To develop an OEIC Packaging many different techniques are necessaryto be mentioned:

  • High Frequency Technology
  • Classical Optics / Wave Optics
  • Precision engineering design and CAD design
  • Refrigeration / heat management
  • Communications Engineering
  • Solid State Physics
  • Etching of silicon substrates
  • Mask techniques
  • Thick film / thin film technology
  • Gluing, soldering, welding, bonding technology

In this course  the fiber chip coupling technology will be analyzed, while new coupling techniques and cost optimization basics are presented. Thus, at the beginning an overview of the technology drivers of optical communications systems will be discussed. Further on many examples of photonic packaging and interconnection technology are presented in depth. All actual adjustment and fixation techniques are focused.
A deeper analysis of the optical interconnection technology with basic theory of waveguide coupling and loss mechanisms concludes the introductory part of the course. Then, an overview on the modular technology of major photonic components in the field of high-rate fiber-optic networks will be presented, followed by the analysis of the fiber-chip coupling in these different applications. In the conclusions a summary and an outlook on the further development of the technology of photonic packaging and interconnection technology will be given.


ULRICH H. P. FISCHER-HIRCHERTHarz University of Applied Sciences, holds Diploma and PhD degree in Physics from the Free University Berlin, Germany. In 2005 he achieved his lecture qualification in photonic  packaging technology at TU Dresden. He has been working on research positions in the Heinrich-Hertz-Institute in Germany. Several international research projects have been performed with European partners from France, Netherlands, Norway and the UK. He is currently Professor of Optical Communications Systems at the Harz University of Applied Sciences, Germany, and CEO of the HarzOptics GmbH. He has edited several books about Photonic Packaging techniques, holds several patents and published more than 100 papers in international scientific journals. His research activity has always been related to Photonic Packaging and Optical Communications Technology. He has been reviewer for several publications of the Optical Society of America's including Photonics Technology Letters and Applied Optics and also at the Deutsche Forschungs Gemeinschaft DFG.

PDC 3 - Understanding Flip Chip Technology and its Applications


This course will cover the fundamentals of flip chip fabrication and assembly processes. It will include all aspects of bumping technology, including SnAgCu solder bumping and Cu Pillar technologies, comparison of various under bump metallurgies (electroplating, electroless plating and sputtering), solder deposition methods, and their applications. Solder joint formation technologies used in single and multi-die assembly of chip scale packages, wafer-level packages, embedded die, chip-on-chip, chip-on-wafer, and 2.5D/3D flip chip packages are discussed and demonstrated through industrial’s leading application examples.  Advanced and current trend of flip chip assembly process are provided briefly. This course will cover the reliability tests commonly used to qualify the flip chip assembled packages, the failure types and the analytical tools, such as sonoscan, solder or die shear, x-ray, and shadow or projection moiré, used for process monitoring and to identify defect root cause.  A substantial portion of this course will be covering the Cu Pillar flip chip technologies. Failure modes, such as barrier consumption, Kirkendall and other solder voids formation mechanisms, contact non-wets, BEOL dielectric cracking, electromigration, etc. will be included dispersedly in the related subjects of the whole course.   The targeted audience includes scientists, engineers and managers currently using flip chip technology (w/solder or Cu Pillar) or considering moving from wire bonding to flip chip, as well as reliability, product or applications engineers who need a deeper understanding of flip chip technologies: the advantages, limitations and failure mechanisms.

Course outline:

  1. Introduction to Flip Chip Technologies
  2. UBM Metal Selection and Solder Deposition Processes
  3. C4 and Cu Pillar Fabrication Issues
  4. Flip Chip Ball Grid Array (FCBGA) Assembly Process Flow
  5. Chip Package Interaction and Electromigration
  6. Flip chip technology new trends: Wafer Level, Panel Level and 2.5D
  7. Substrate Technologies and Characterization Methods


ERIC PERFECTO, Globalfoundries, has 36 years of experience working in the development and implementation of advanced packages. He is currectly Principal Member of the Technical Staff at GLOBALFOUNDRIES. He holds an M.S. in Chemical Engineering from the University of Illinois and an M.S. in Operations Research from Union College. Eric has published over 75 papers, holds over 45 US patents, and has been honored with two IBM Outstanding Technical Achievement Awards and an IBM Outstanding Contribution Award for the Development of 3D Wafer Finishing Process. Eric was the 57th ECTC General Chair in Reno, NV, and the Program Chair at the 55th ECTC.  He is an IEEE Fellow, a Distinguish Lecturer of the EPS society of IEEE, and the EPS Awards Program Director.

PDC 4 - From Wafer to Panel Level Packaging


Panel Level Packaging (PLP) is one of the latest trends in microelectronics packing. Besides technology developments towards heterogeneous integration including multiple die packaging, passive component integration in package and redistribution layer or package-on-package approaches also larger substrates formats are targeted. Manufacturing is currently done on wafer level up to 12”/300 mm and 330 mm respectively. For higher productivity and therewith lower costs larger form factors are introduced. Instead of following the wafer level roadmaps to 450 mm, panel level packaging might be the next big step. Sizes considered for the panel range from 300x300 mm² to 457x610 mm³ or 510x515 mm² up to 600x600 mm² or even larger. Additionally PLP has the opportunity to adapt processes, materials and equipment from other technology areas. Printed Circuit Board (PCB), Liquid Crystal Display (LCD) or solar equipment is manufactured on panel sizes and offer new approaches also for Fan-out Panel Level Packaging (FOPLP).

However, an easy upscaling of technology when moving from wafer to panel level is not possible. Materials, equipment and processes have to be further developed or at least adapted. A view along the process chain offers lots of possibilities but also challenges. Starting from carrier material selection for a chip first approach where not only the thermo-mechanical behavior but also properties as e.g. weight or stability should be considered. Pick and place assembly on carrier is independent from wafer or panel formats a bottleneck. Here new equipment or even new approaches for high speed but also high accuracy assembly are required. Compression molding is typically used for chip embedding and to form the reconfigured wafer or panel. Liquid, granular and sheet type molding compounds are available. All allowing chip embedding with pros and cons in cost, processability but also in cleanroom compatibility. For redistribution layer (RDL) formation a large variety of lithography tools and dielectric material options exist. As dielectrics photosensitive as well as non-photosensitive or liquid versus dry-film materials can be considered. Mask-based lithography as e.g. stepper technology is just as maskless based tools as laser direct imaging (LDI) available for panel sizes. Both offering different capabilities and strategies to overcome challenges from die placement accuracy and die shift after molding. Finally also solutions for grinding, balling and singulation are needed. Handling and especially automated handling of molded large panels including also storage and transport is still an open topic as until now only custom-made solutions exist.

The PDC will give a status of the current Fan-in and Fan-out Wafer Level Packaging as well Panel Level Packaging. This will include material discussion, technologies, applications and market trends as well as cost modelling.


TANJA BRAUN, Fraunhofer IZM, studied mechanical engineering at Technical University of Berlin with a focus on polymers and micro systems and joined Fraunhofer IZM in 1999. Since 2000 she is working with the group Assembly & Encapsulation Technologies and since 2016 she is head of this group. Her field of research is process development of assembly and encapsulation processes, the qualification of these processes using both non-destructive and destructive tools and advanced polymer analysis. Recent research is focused on wafer and panel level packaging technologies and Tanja Braun is leading the Fan-out Panel Level Packaging Consortium at Fraunhofer IZM Berlin. In 2013 she received her Dr. degree from the Technical University of Berlin for the work focusing on humidity diffusion through particle-filled epoxy resins.

MICHAEL TÖPPER, Fraunhofer IZM, has a M.S. degree in Chemistry and a PhD in Material Science. Since 1994 he is with the Packaging Research Team at TU Berlin and Fraunhofer IZM. In 1997 he became head of a research group. In 2006 he was also a Research Associate Professor of Electrical and Computer Engineering at the University of Utah, Salt Lake City. The focus of his work was Wafer Level Packaging applications with a focus on materials. Since 2015 he is part of the business development team at Fraunhofer IZM. Michael Töpper is Senior Member of IEEE-CPMT and has received the European Semi-Award in 2007 for WLP. He has published several book chapters and is author and co-author of over 200 publications.